Method for forming interconnection levels of an integrated circuit

ABSTRACT

A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of French patentapplication number 08/52035, filed on Mar. 28, 2008, entitled “METHODFOR FORMING INTERCONNECTION LEVELS OF AN INTEGRATED CIRCUIT,” which ishereby incorporated by reference to the maximum extent allowable by law.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an integrated circuit and, morespecifically, to a method for forming interconnection levels of anintegrated circuit.

2. Discussion of the Related Art

Integrated circuits are comprised of a large number of electroniccomponents which are formed in and on a semiconductor wafer. To properlyconnect these components, several interconnection levels form the upperportion of the integrated circuits. Each interconnection level comprisesconductive tracks. Vias are formed to connect conductive tracks ofdifferent interconnection levels.

FIG. 1 is a cross-section view of an example of the stack of severalinterconnection levels (N_(j), N_(i+1), N_(i+2) . . . ) of an integratedcircuit, level N₁ being the interconnection level closest to theelectronic components.

Each interconnection level N_(i) comprises a portion M_(i) in which areformed conductive tracks 10, located above a portion V_(i) in which areformed vias 12 of contact between tracks of adjacent levels (currently,the vias of interconnection level N₁ are of a different nature than thevias of the other levels). In this drawing, the cross-section plane issuch that the tracks are cut widthwise, so that conductive tracks 10appear to be of same cross-section area as vias 12. Vias 12 enableproperly connecting two conductive tracks 10 located in two neighboringinterconnection levels. As an example, tracks 10 and vias 12 may be madeof copper. A dielectric material 14 separates tracks 10 from one anotherand vias 12 from one another.

Nowadays, electronic components formed in integrated circuits operate athigher and higher frequencies. The frequency increase results in anincrease in the values of the stray capacitances which form between thedifferent conductive portions. Further, the continuous miniaturizationof electronic components results in a decrease in the size of conductivetracks and a decrease in distances between tracks and between vias,which also increases the values of stray capacitances. Straycapacitances may disturb significantly the operation of a circuit. It isthus desired to decrease as much as possible such stray capacitancesand, for this purpose, so-called “low-k” dielectric materials havingvery low relative permittivities, typically smaller than 3, are usedbetween the different conductive portions.

However, the porosity of dielectric material 14 poses various problems.Especially, the copper of conductive tracks 10 diffuses more easily intoporous dielectric materials than into non-porous dielectric materials.To limit such a diffusion, it is particularly useful to form, betweentwo neighboring interconnection levels, a layer 16 which,conventionally, stops the diffusion of conductive material from aninterconnection level to the dielectric material of the upperinterconnection level and which forms an etch stop layer. Vias 12 crosslayer 16. As an example, layer 16 may be made of silicon-carbon nitride(SiCN). It has also been provided to form a barrier layer (not shown)around the conductive tracks and the vias, this layer being made of aconductive material capable of avoiding the diffusion of the conductivematerial present in an interconnection level towards the porousdielectric material of the same interconnection level. This barrierlayer is, for example, formed of tantalum and of tantalum nitride.

Further, on manufacturing of the stack of interconnection levels,various etch and/or polishing and cleaning operations are carried out inliquid or gas phase. Contaminating products may thus penetrate into thepores of the porous dielectric material during these operations. Thismay cause an alteration of the porous material or an increase in itsrelative permittivity, which limits the advantage of using such a porousmaterial.

A way to restore the characteristics of the porous material comprisesperforming, after having formed each interconnection level, an anneal toeliminate the contaminating products present in the porous dielectricmaterial.

FIG. 2 is a cross-section view illustrating a stack of twointerconnection levels N_(i) and N_(i+1). This drawing illustrates theresult obtained after having carried out a chem./mech. polishing step(CMP) on the structure and an anneal step aiming at eliminating thecontaminating products present in interconnection level N_(i+1). Theconductive tracks of the two interconnection levels are shown lengthwisein cross-section view.

Interconnection level N_(i) comprises conductive tracks 20 surroundedwith a porous dielectric material 22. The bottom and the walls ofconductive tracks 20 are covered with a thin barrier layer 24 of amaterial avoiding the diffusion of conductive material from conductivetracks 20 to porous dielectric material 22. A thin layer 26 of amaterial avoiding the diffusion of conductive material from conductivetracks 20 to interconnection level N_(i+1), for example, made of SiCN,extends above interconnection level N_(i). Interconnection levelN_(i+1), which comprises conductive tracks 28 connected by vias 30 toconductive tracks 20 of interconnection level N_(i) is formed above thinlayer 26. A porous dielectric material 32 separates conductive tracks 28from one another and vias 30 from one another. The walls and the bottomof conductive tracks 28 and of vias 30 are covered with a thin barrierlayer 34 of a conductive material. Interconnection levels N_(i) andN_(i+1) may be obtained by different known methods.

On forming of interconnection level N_(i+1), the etch and/or polishingand cleaning steps cause the contamination of porous dielectric material32. An additional step, where an anneal of the structure is performed toenable evaporation of the contaminants, is then carried out. As anexample, this anneal step may be carried out at a temperature ofapproximately 300° C. for approximately 30 minutes. This anneal needs tobe performed before deposition of a layer homologous to layer 26 whichwould create a barrier against the evaporation of contaminants.

In FIG. 2, arrows 36 illustrate the evacuation, during the anneal, ofthe contaminating products present in porous dielectric material 32.Although the anneal enables eliminating the contaminating productspresent in porous dielectric material 32, it should be noted that italso causes the expansion of the conductive material of conductivetracks 28. This expansion modifies the upper surface of conductivetracks 28 and makes it rough. Problems, for example, in terms ofreliability, may then arise when another interconnection level isdesired to be formed on the upper surface of interconnection levelN_(i+1). Further, since porous dielectric material 32 is not protectedon its upper surface, it is contaminated again by the contact with theair, especially by water vapor, when the structure is taken out of thefurnace in which the anneal has been performed. This recontamination isillustrated in FIG. 2 by arrows 38.

To limit the expansion of the conductive material, the annealtemperature is may be decreased. However, a decrease in the annealtemperature causes an increase in the duration of this anneal anddecreases its efficiency.

SUMMARY OF THE INVENTION

At least one embodiment of the present invention aims at providing amethod for forming interconnection levels of an integrated circuitenabling avoiding at least some of the problems of prior art methods.

Thus, an embodiment of the present invention provides a method forforming interconnection levels of an integrated circuit, comprising thesteps of:

(a) forming an interconnection level comprising conductive tracks andvias separated by a porous dielectric material;

(b) forming, on the interconnection level, a layer of a non-porousinsulating material, said layer comprising openings above portions ofporous dielectric material;

(c) repeating steps (a) and (b) to obtain the adequate number ofinterconnection levels; and

(d) annealing the structure.

According to an embodiment of the present invention, an anneal step isperformed before each repetition at step (c).

According to an embodiment of the present invention, step (a) offormation of an interconnection level comprises the steps of

forming a layer of a porous dielectric material;

forming an oxide layer, then a titanium nitride layer on the layer ofporous dielectric material;

forming openings in the titanium nitride layer and in an upper portionof the oxide layer at the level of the desired conductive tracks;

forming holes in the oxide layer and in an upper portion of the layer ofporous dielectric material at the level of the desired vias;

etching, outside the areas covered with the titanium nitride layer,until the bottom of the holes reaches the conductive tracks of the lowerinterconnection level;

forming a conductive material in the etched portion; and

removing the materials located above the layer of porous dielectricmaterial.

According to an embodiment of the present invention, the step of formingholes and the step of etching outside the areas covered by the titaniumnitride layer are etch steps in the presence of argon and of C₄F₈.

According to an embodiment of the present invention, the removal of thematerials located above the layer of porous dielectric material isperformed by chem./mech. polishing (CMP).

According to an embodiment of the present invention, the layers of nonporous insulating material are made of silicon-carbon nitride (SiCN) andthe conductive tracks and the vias are made of copper.

An embodiment of the present invention provides an integrated circuitcomprising a stack of interconnection levels, each interconnection levelcomprising conductive tracks, conductive tracks of differentinterconnection levels capable of being connected by vias, theconductive tracks and the vias being separated by porous dielectricmaterials, non-porous insulating layers crossed by the vias being formedon the different interconnection levels, said non-porous insulatinglayers comprising openings located on portions of porous dielectricmaterials.

According to an embodiment of the present invention, the porousdielectric materials have thicknesses ranging between 100 and 250 nm.

According to an embodiment of the present invention, the layers ofnon-porous insulating material are made of silicon-carbon nitride (SiCN)and the conductive tracks and the vias are made of copper.

According to an embodiment of the present invention, the openings in thenon-porous insulating layers have dimensions greater than 70 nm.

The foregoing and other objects, features, and advantages of the presentinvention will be discussed in detail in the following non-limitingdescription of specific embodiments in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, previously described, is a cross-section view of severalinterconnection levels of an integrated circuit;

FIG. 2, previously described, illustrates the result obtained afterhaving performed an anneal on an interconnection level N_(i+1); and

FIGS. 3A to 3I are cross-section views illustrating steps of a methodfor manufacturing a stacking of interconnection levels according to anembodiment of the present invention.

DETAILED DESCRIPTION

For clarity, the same elements have been designated with the samereference numerals in the different drawings and, further, as usual inthe representation of integrated circuits, the various drawings are notto scale.

FIGS. 3A to 3I are cross-section views illustrating results of steps ofa method for manufacturing a stack of interconnection levels accordingto an embodiment of the present invention. FIGS. 3A to 3G are drawnalong a first cross-section plane and FIGS. 3H and 3I along a secondcross-section plane.

In FIG. 3A, it is started from a structure in which an interconnectionlevel N_(i) has already been formed. Interconnection level N_(i)comprises conductive tracks 40, two of these tracks being shownlengthwise in cross-section view in FIG. 3A. As an example, conductivetracks 40 may be made of copper. Vias (not shown) may also be formed toconnect conductive tracks 40 to tracks of lower level. Conductive tracks40 are separated by a porous dielectric material 42. The walls and thebottom of conductive tracks 40 are covered with a thin barrier layer 44of a conductive material which prevents the diffusion of copper fromconductive tracks 40 to porous dielectric material 42. Aboveinterconnection level N_(i) is formed a non-porous thin insulating layer46, for example, made of SiCN, which prevents the diffusion of copperfrom tracks 40 to interconnection level N_(i+1) which will be formedabove insulating layer 46.

According to an aspect of the present invention, non-porous insulatinglayer 46 comprises openings 48 located above portions of porousdielectric material 42, a single one of openings 48 being shown in FIG.3A. Openings 48 are formed above portions of interconnection level N_(i)having a low density of conductive tracks 40.

At the step illustrated in FIG. 3B, a thicker layer of porous dielectricmaterial 50 has been formed on thin non-porous insulating layer 46. Asan example, layer 50 of porous dielectric material may be obtained byintroducing a pore-forming agent into a thick layer of non-porousdielectric material, then reacting the pore-forming agent, for example,by anneal, to eliminate the pore-forming agent and form the pores of theporous dielectric material. On top of layer 50 of porous dielectricmaterial is formed a stack of two layers 52 and 54 which behave as masksin subsequent steps. As an example, layer 52 is a deposited siliconoxide layer and layer 54 is a titanium nitride layer (TiN).

At the step illustrated in FIG. 3C, openings 56 have been formed intitanium nitride layer 54, these openings extending slightly into oxidelayer 52. The contour of openings 56 defines the contour of theconductive tracks which will be formed in interconnection level N_(i+1).As an example, openings 56 may be formed by depositing a resist ontitanium nitride layer 54, by appropriately insolating and etching thisresist, and by etching layers 52 and 54. Layer 52 is only partiallyetched to avoid any direct contact between the resist and porousdielectric material 50 during the next step.

At the step illustrated in FIG. 3D, holes 58 which cross oxide layer 52and an upper portion of layer 50 of porous dielectric material have beenformed in openings 56. Holes 58 define the contour of the vias whichwill be formed in s interconnection layer N_(i+1). Holes 58 may beobtained, by means of an adapted mask, by a physico-chemical etchingperformed in the presence of argon and of C₄F₈. Further, a hydrofluoricacid (HF) cleaning step is carried out after the etching. During theetching and the cleaning, contaminating products (for example, fluorine)penetrate into the pores of porous dielectric material 50, as loillustrated in FIG. 3D by arrows 60.

At the step illustrated in FIG. 3E, an etching of the portion of oxidelayer 52 and of layer 50 of porous dielectric material which are notprotected by titanium nitride layer 54 has been performed. As anexample, this etching may again be a physico-chemical etching in thepresence of argon and of C₄F₈, followed by a cleaning with hydrofluoricacid. This etch step enables forming the contour of the conductivetracks and of the vias of interconnection level N_(i+1). It is performedso that holes 58 cross thin SiGN layer 46 and that they reach conductivetracks 40 of interconnection level N_(i). In the same way as in theprevious etch step, contaminating products penetrate into porousdielectric material 50, during the etching and the cleaning, asindicated by arrows 62 in FIG. 3E.

At the step illustrated in FIG. 3F, the space created in the previousetch step has been filled with a conductive material to form conductivetracks 64 and vias 65 of interconnection level N_(i+1). The conductivematerial of conductive tracks 64 and of vias 65 may be copper, and themetallization is carried out so that the copper fills the spacescontacting conductive track inductive material avoiding the diffusion ofcopper from conductive layers 64 and vias 65 to the neighboring porousdielectric material 50 may be formed before the metallization.

At the step illustrated in FIG. 3G, a chem./mech. polishing (CMP) forremoving the excess copper and tantalum nitride 66 located above layer50 of porous dielectric material, as well as titanium nitride layer 54and oxide layer 52, has been carried out. In the same way as in the etchsteps, during the polishing step and the subsequent cleaning step,contaminating products may penetrate into porous dielectric material 50,as illustrated in FIG. 3G by arrows 68.

FIGS. 3H to 3I illustrate subsequent steps of the manufacturing methodaccording to an embodiment of the present invention, in a cross-sectionplane different from that of FIGS. 3A to 3G. In these drawings, allconductive tracks appear lengthwise in cross-section view and thedifferent barrier layers (especially 44 and 66) have not been shown forthe simplification.

FIG. 3H illustrates a structure substantially identical to that of FIG.3G. In this drawing, interconnection levels N_(i) and N_(i+1) compriseseveral conductive tracks 40, 64 and several vias 65. Aboveinterconnection level N_(i+1) is formed a non-porous insulating layer70, for example, made of SiGN.

According to an aspect of the present invention, non-porous insulatinglayer 70 comprises openings 72 above portions of porous dielectricmaterial 50. In FIG. 3H, a single one of openings 72 is shown. Openings72 are formed above portions of interconnection level N_(i+1) having alow density of conductive tracks 64.

At the step of FIG. 3I, an interconnection level N_(i+2) has been formedon thin SiCN layer 70. Interconnection level N_(i+2) may be formed inthe same way as interconnection level N_(i+1). Interconnection levelN_(i+2) comprises conductive tracks 74 and vias 76, the tracks and viasbeing separated by a porous dielectric material 78.

On top of interconnection level N_(i+2) is formed a thin non-porousinsulating layer 80, for example, made of SiCN, which comprises openings82 above portions of porous dielectric material 78. In FIG. 3I, a singleone of openings 82 has been shown. In the same way as for openings 48and 72, openings 82 are formed above portions of interconnection levelN_(i+2) with a low density of conductive tracks.

Preferably, after the forming of each opening 48, 72, and 82 in SiCNlayers 46, 70, and 80 on interconnection levels N_(i), N_(i+1), andN_(i+2), an anneal of the structure enabling evaporation of thecontaminating products present in the porous dielectric materials,respectively 42, 50 and 78, of these levels, is performed.

In FIG. 3I, the circulation of contaminating products during an annealintended to eliminate contaminating products from interconnection levelN_(i+2) has been shown. The contaminating products present in layer 78of porous dielectric material tend to evaporate and to come out throughopening 82, as shown by arrows 84. It should be noted that thecontaminating products go round vias 76 of interconnection levelN_(i+2). Further, this anneal also allows for contaminating productspresent in the lower levels to migrate upwards in the structure, fromlevel to level, via openings 48, 72 formed in non-porous insulatinglayers 46, 70, as shown by arrows 86, and to escape from the structurethrough openings 82 of non-porous insulating layer 80.

Non-porous insulating layers 46, 70, and 80 covering conductive tracks40, 64, and 74 prevent the expansion of the conductive material of thesetracks. This enables annealing at temperatures higher than thosecurrently used and thus enables better evacuation of contaminatingproducts. Further, the recontamination of the porous dielectric materialafter the anneal steps only occurs in regions with a low density ofconductive materials, which does not increase stray capacitances inremote regions with a high density of conductive tracks.

Non-porous insulating layers 46, 70, and 80 may be made of anynon-porous insulating material, but they will preferably be made ofsilicon-carbon nitride SiCN, this material stopping the passing ofcontaminating products and also avoiding diffusion of the material ofconductive tracks 40, 64, and 74 towards the porous dielectric materialof the upper levels.

As an example, layers 42, 50, 78 of porous dielectric material havethicknesses ranging between 100 and 250 nm. As an example also, theopenings may have dimensions, sides or diameters greater than 70 nm.

Specific embodiments of the present invention have been described.Various alterations, modifications, and improvements will occur to thoseskilled in the art. In particular, it should be understood that theanneal steps may be carried out after having formed severalinterconnection levels. Two interconnection levels or more may forexample be formed before performing an anneal to evacuate thecontaminating products from these two levels. A longer anneal step mayalso be provided once all interconnection levels have been formed toenable evaporation of the contaminating products remaining in thedifferent interconnection levels.

Openings 48, 72, and 82 may be formed above one another or in shiftedfashion, as shown in FIG. 3I.

Further, a specific method for forming an interconnection levelcomprising tracks and vias has been described, in which the conductivematerial of the tracks and vias is formed in a single step. It should beunderstood that the tracks and vias of each interconnection level may beformed separately and by any known method.

As an example, porous dielectric material 42, 50, 78, may be “BDIIx”, amaterial sold by Applied Materials.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

1. A method for forming a stack of interconnection levels of anintegrated circuit, comprising the steps of: (a) forming aninterconnection level comprising conductive tracks formed aboveconductive vias, the tracks and the vias being laterally separated by aporous dielectric material; (b) forming, on the interconnection level, alayer of a non-porous insulating material, said layer comprisingopenings formed only above portions of porous dielectric material; (c)repeating steps (a) and (b) to obtain the adequate number ofinterconnection levels of the stack, the conductive vias of aninterconnection level of the stack having another interconnection levelbelow contacting the conductive tracks of the interconnection levelbelow; and (d) annealing the structure.
 2. The method of claim 1,wherein an anneal step is performed before each repetition at step (c).3. The method of claim 1, wherein step (a) of formation of aninterconnection level comprises the steps of: forming a layer of aporous dielectric material; forming a silicon oxide layer, then atitanium nitride layer on the layer of porous dielectric material;forming openings in the titanium nitride layer and in an upper portionof the oxide layer at the level of the desired conductive tracks;forming, at the bottom of the openings, holes in the oxide layer and inan upper portion of the layer of porous dielectric material at the levelof the desired conductive vias; etching, outside the areas covered withthe titanium nitride layer, until the bottom of the holes reaches theconductive tracks of the lower interconnection level; forming aconductive material in the etched portion; and removing the materialslocated above the layer of porous dielectric material.
 4. The method ofclaim 3, wherein the step of forming holes and the step of etchingoutside the areas covered by the titanium nitride layer are etch stepsin the presence of argon and of C₄F₈.
 5. The method of claim 3, whereinthe removal of the materials located above the layer of porousdielectric material is performed by chem./mech. polishing.
 6. The methodof claim 1, wherein the layers of non porous insulating material aremade of silicon-carbon nitride and the conductive tracks and theconductive vias are made of copper.
 7. An integrated circuit comprisinga stack of interconnection levels, each interconnection level of thestack comprising conductive tracks and conductive vias, conductivetracks of different interconnection levels being adapted to be connectedby the vias, the tracks and the vias of a same interconnection levelbeing laterally separated by porous dielectric materials, non-porousinsulating layers crossed by the vias being formed on eachinterconnection level, said non-porous insulating layers comprisingopenings located only on portions of porous dielectric materials.
 8. Theintegrated circuit of claim 7, wherein the porous dielectric materialshave thicknesses ranging between 100 and 250 nm.
 9. The integratedcircuit of claim 7, wherein the layers of non-porous insulating materialare made of silicon-carbon nitride and the conductive tracks and theconductive vias are made of copper.
 10. The integrated circuit of claim7, wherein the openings in the non-porous insulating layers havedimensions greater than 70 nm.